Scaling down transistor channel lengths is the most important ingredient fueling the last twenty years progress of semiconductor industry. The width-to-length (W/L) ratio of transistors is directly proportional to the transistors on-current. The channel length L is a more important parameter in typical scaling rules since the circuit switch speed can be scaled down with smaller length L but not with larger width W.
However, conventional methodology in semiconductor industry of scaling down transistor channel lengths is to use high-resolution lithography tool to define transistor critical dimensions (e.g., gate length, source/drain separations) with their finest resolution. The shortest channel length is therefore directly limited by the tools, and it is very difficult and expensive to realize high resolution lithography tools for large-area process. Current multi-million large area lithography tools for LCD back-plane manufacturing have typical resolution limits around 2 μm, which is more than one orders of magnitude larger than the state-of-the-art photolithography tool designed for crystalline Si industry. The recent development of feature patterning techniques based on patterning technology has even lower resolution limits, e.g., about 40 um for wax inkjet printing technique, 100 um for screen printing technique, 100 um for PCB dry film resist technique.
There are a few high resolution, relatively low cost un-conventional feature patterning techniques under development that rely on contact pattern transferring, which must be carefully studied for the known problems of contact pattern transferring such as mask life time and particle defect propagation before these methods can be adopted by the industry.
Another conventional technique for scaling down transistor channel length without using high resolution lithography is the formation of vertical transistor structures. This methodology claims to use layer thickness, which is the most controllable dimension in the large area process, to define transistor channel length. However, the problems of most proposed vertical transistor structures are the large parasitic capacitance and parasitic conductance between source and drain contacts, caused by the overlap of source and drain electrodes, which are defined by the resolution of lithography tools.
What is needed is a highly reliable method for producing integrated circuits having high resolution features using relatively low resolution feature patterning (e.g., lithography) tools that is both economical and reliable.